Moore's Law scaling dictates that the number of transistors within an integrated circuit (IC) essentially double from technology node to technology node, and consequently the chip area required to for a fixed number of transistors be cut in half for silicon cost savings and increased performance. This drives a decrease the minimum feature pitch within the IC for increased feature density. To achieve this, multiple-patterning processes may be utilized in for patterning of features formed on front-end-of-line (FEOL) layers (e.g., polysilicon gate materials) and back-end-of-line (BEOL) layers (e.g., metal wiring) in advanced technology node semiconductor manufacturing processes.